1. Field of the Invention
This invention relates to integrated circuit manufacturing and more particularly to semiconductor wafer handling associated with wafer fabrication.
2. Description of the Relevant Art
A typical modern wafer fabrication process forms multiple integrated circuits upon each of several semiconductor wafers processed one after another (i.e., sequentially). During wafer fabrication, multiple die areas are defined upon frontside surfaces of the semiconductor wafers. Integrated circuits are formed within these die areas using a series of wafer fabrication operations (e.g., layering, patterning, doping, and heat treatments). Following wafer fabrication, the dice are separated from the semiconductor wafers. Fully functional dice are typically mounted within semiconductor device packages and sold as individual units.
Due to the imperfect nature of all manufacturing processes, flaws or defects are introduced into integrated circuits during wafer fabrication. Sources of defects which adversely affect integrated circuit yield, performance, or reliability must be discovered and eliminated. Many such defects are caused by the introduction of one or more contaminants into integrated circuits during wafer fabrication operations. Such contaminants include small particles (i.e., particulates), heavy metal atoms, and mobile ionic contaminants.
Particulates are present in the ambient air, introduced by processing personnel, suspended in liquids and gasses used during processing, and generated by processing equipment. Particulates typically cause defects during layering and patterning operations. Particulates on the surface of a wafer may prevent the formation of a uniform layer of a desired material upon that surface. Such particulates also block or diffuse light during patterning operations (i.e., photolithography), causing imperfect pattern registrations resulting in imperfect feature formations.
Heavy metals include iron (Fe), copper (Cu), nickel (Ni), and gold (Au). Atoms of heavy metals form sites where minority and majority charge carriers have a tendency to recombine (i.e., recombination centers). As a result, minority carrier lifetimes are reduced. In general, long minority carrier lifetimes are beneficial to semiconductor device operation. Recombination centers which exist within regions near a surface of a semiconductor wafer where active devices reside (i.e., device active areas) thus represent defects as they lead to reduced minority carrier lifetimes.
Heavy metal contaminants may be derived from processing equipment during wafer fabrication. For example, many of the components which make up wafer fabrication tools are made of stainless steel, including ion implanters and gas and liquid delivery lines. Thus heavy metal atoms comprising stainless steel species may be introduced into semiconductor wafers during ion implantation and other wafer fabrication operations.
The presence of mobile ionic contaminants (e.g., sodium and potassium ions) in dielectric layers of metal oxide semiconductor (MOS) devices are known to cause device reliability problems. Mobile ionic contaminants are present in water and chemicals used during wafer fabrication, and also may be introduced by processing personnel. Ionized sodium (Na.sup.+) and potassium (K.sup.+) atoms are very mobile in oxide layers, and tend to move through gate oxides of MOS devices under the influence of the electric fields generated between gate electrodes and substrates during device operation. Long term changes in MOS device threshold voltage levels may occur as the charged ions drift to the interface between the gate oxide and the underlying substrate. Changes in threshold voltage levels may become large enough to cause circuits which incorporate these MOS devices to fail to meet electrical or performance requirements.
In order to determine the source of a given defect, test wafers are often included with wafers expected to yield operational integrated circuits (i.e., product wafers) and subjected to one or more wafer fabrication operations. Following the one or more wafer fabrication operations, the test wafers are separated from the product wafers and examined in an effort to determine the source of the defect. Such test wafers, however, represent a reduction in manufacturing yield as they do not produce operational devices.
An alternate approach to defect diagnosis which takes advantage of the sequential nature of modern wafer processing operations is to process the semiconductor wafers in a unique order through each wafer fabrication tool (e.g., deposition chamber, etch chamber, furnace, diffusion chamber, ion implantation device, etc.). Take, for example, a wafer fabrication tool which introduces contaminants into processed wafers. Due to sequential processing, the number of contaminants (or defects) in a given wafer corresponds to the order in which the wafer was processed through the wafer fabrication tool. A graph of contaminant (or defect) levels versus processed wafer number displays a consistent increasing contaminant (or defect) level trend. Thus if a group of wafers are processed through each of several wafer fabrication tools, and one of the wafer fabrication tool introduces more contaminants than the others, and the order in which each of the wafers is processed is unique for each wafer fabrication tool, then arrangement of the contaminant (defect) levels corresponding to each wafer in increasing order reveals the unique wafer processing sequence of the wafer fabrication tool which introduces the most contaminants.
A typical wafer fabrication facility includes multiple wafer fabrication tools which perform various wafer fabrication operations upon groupings of semiconductor wafers called "lots". The semiconductor wafers are typically transported within containers called wafer cassettes or wafer "boats". Each wafer cassette is configured to hold several wafers. Wafer fabrication tools typically incorporate wafer handling systems which remove wafers from cassettes for processing in a fixed order (e.g., first to last, top to bottom, etc.) and return processed wafers to their original positions within the cassettes.
The above approach to defect diagnosis is commonly implemented using special wafer fabrication tools called "wafer sorters" which do nothing but rearrange wafers within wafer cassettes so as to form unique orderings of the wafers within the cassettes. The unique orderings of the wafers within the cassettes are then recorded and associated with the wafer fabrication tool which is to process the wafers next, a necessary step in the above defect diagnosis approach. A wafer sorter must be visited prior to processing by each wafer fabrication tool. Multiple wafer sorters may thus be required to reduce processing bottlenecks. In addition to the initial costs of the wafer sorters, visits to wafer sorters add time to the overall wafer fabrication process and expose wafers to additional risks of damage or contamination.
It would thus be desirable to have a wafer fabrication tool which incorporates a wafer handling system capable of processing wafers within a wafer cassette in any order. Such desired wafer fabrication tools may be used to implement the above defect diagnosis approach which does not require test wafers or dedicated wafer sorters. The use of such desired wafer fabrication tools would also reduce overall wafer fabrication times as well as eliminate the additional risks of wafer damage or contamination associated with the wafer sorters.